Packaging for microelectronic devices is facing increasing demand for smaller dimensions. This trend is driven by consumer demand for increasing portability of computing devices such as smart phones and laptops. Currently, there is an industry-wide trend to reduce Integrated Circuit (IC) package dimensions to accommodate the trend for ultrathin high performance smart phones, where IC package thickness, as well as footprint, is reduced without impacting device performance. However, increasingly thinner packages are subject to high warpage, drastically impacting yield.